1. Field of the Invention
The present invention relates to a method of forming a metal wiring layer of a semiconductor device.
2. Description of the Related Art
The line widths of wiring patterns of semiconductor devices are being made smaller and smaller to increase the degree of integration of the devices. The wiring patterns are constituted by a series of metallic lines. Conventionally, metal wiring patterns were formed by depositing metal on an insulting layer and then patterning the resultant metal layer. However, patterning a metal layer to produce a pattern of very narrow lines is difficult. An example of an alternative method capable of forming a pattern of metal lines having a very small line width is a damascene process.
The damascene process basically entails forming recesses, e.g., trenches, in an insulating layer and then filling the recesses with metal such as Al. In general, such a damascene process comprises forming an Al layer serving as a seed layer in the recesses by chemical vapor deposition (CVD) process, depositing Al thereon by physical vapor deposition (PVD), and then conducting a high temperature treatment of the resultant structure to grow the Al crystals and thereby form Al wiring in the recesses. The critical dimension (CD), namely the line width, of the wiring formed by a damascene process can be 100 nm or less.
However, a pinch off phenomenon may occur when wiring having such a minute line width is formed using a damascene process. More specifically, the pinch off phenomenon is one in which an inlet of a recess in the insulating layer is closed by Al during the CVD process, i.e., before the PVD process is carried out. In this case, a void is formed in the recessed region. Therefore, the resistance of the wiring is relatively high. Accordingly, the semiconductor device may not operate stably, and the wiring of the semiconductor device may even experience a short circuit during use.
In addition, an IMD (InterMetallic Dielectric) layer is formed on an upper portion of the damascene wiring. Then contact or via holes are formed in the IMD layer. The contact or via holes extend to and expose the damascene wiring so that the wiring may be connected to an upper metallic layer. Basically, the contact or via holes are formed by etching the IMD layer. However, the Al wiring may be etched when the IMD layer is etched because there is almost no etch selectivity between the oxide of the IMD layer and the Al of the wiring layer. That is, the damascene wiring may be damaged during the etching of the IMD layer. In particular, short circuits are likely to occur in a thin damascene wiring that has been etched during the forming of the contact or via holes. Accordingly, it is difficult to manufacture a reliable semiconductor device whose wiring has a minute line width.